1. Field of the Invention
This invention relates to field effect transistor driver circuits and more particularly, to an enhancement/depletion mode FET circuit in which high speed full output voltage swing signals are provided with minimal power dissipation.
2. Description of the Prior Art
An example of an enhancement/depletion mode field effect transistor driver circuit is found in the crossreferenced publication by the inventor of the present invention. As shown in the publication, a pair of enhancement mode field effect transistors are connected in series across a supply potential with an output taken from an output node therebetween. The signals applied to the gates of the two series connected output transistors are out of phase to minimize the flow of direct current across the power supply terminals. Also illustrated in the publication are depletion mode devices receiving an input signal at their gating electrodes.
A known advantage of depletion mode field effect transistor devices is that the "threshold voltage" drop associated with enhancement mode field effect transistor devices is eliminated. The advantages of "switched" depletion mode devices over self-biased depletion mode devices include positive timing control and reduced rise delay. One solution to the "threshold voltage drop" problem in enhancement mode devices has been the use of a gate to source bootstrap capacitor as described, for example, in Polkinghorn U.S. Pat. No. 3,506,851. In that patent, however, only one of the series connected output transistors has its gate connected to an input signal and no depletion mode devices are described. As described in the foregoing specific references and numerous others, the prior art has strived to provide high speed output signals with a full supply voltage swing with minimal power dissipation.